With development of technology, semiconductor devices continuously advance toward high integration and high speed and are used in a variety of products from large home appliances to small mobile products.
FIG. 1 is a block diagram showing a structure of a circuit for cutting off supply of external power in a conventional semiconductor memory device.
The conventional semiconductor memory device includes, as shown in FIG. 1, an internal circuit 1 connected to be driven between an external power VDD and a ground power and a PMOS transistor P1 which controls the supply of the external power VDD in response to a deep power down mode signal SDPD.
The internal circuit 1 includes every circuit inside the semiconductor memory device such as an input buffer, a command decoder, a word line signal generating circuit, a cell block and a data pad.
The PMOS transistor P1 is provided between the external power VDD and the internal circuit 1 and cut off the supply of the external power VDD to reduce the leakage current generated in the internal circuit 1 in the deep power down mode. That is to say, when the internal circuit is entered into the deep power down mode, the deep power down mode signal becomes a high level and the PMOS transistor P1 is turned off to cut off the supply of the external power.
However, besides the leakage current generated in the deep power down mode, leakage current generated in a standby condition is also an issue. Particularly, as a transistor with low threshold voltage is used in order to raise an operation speed of the semiconductor memory device, a response speed is improved, whereas the leakage current in the standby condition is more increased.